Expose Total Store Ordering to applications

Originator:akihiko.odaki
Number:rdar://FB13758633 Date Originated:Apr 27, 2024 at 5:01 PM
Status:Open Resolved:
Product:macOS Product Version:
Classification:Suggestion Reproducible:
 
I am a developer of QEMU emulator. While Rosetta 2 works great for running Intel macOS applications on Apple Silicon, some users need more capabilities such as emulating an entire machine for a different guest operating system or emulating architectures other than Intel. QEMU offers such capabilities.
QEMU however cannot provide decent performance for a multi-threaded Intel guest on an Apple Silicon host because of the memory model of Apple Silicon that is relaxed than one of Intel (Total Store Ordering). To overcome this memory model difference, QEMU has to insert barriers for each memory access that significantly damages the performance.
On the contrary, Rosetta 2 does not suffer from the memory model difference. Please expose the underlying mechanism that enables Total Store Ordering for Rosetta 2 for user applications to improve the performance of QEMU on macOS.

Comments

The QEMU project tracks the issue at: https://gitlab.com/qemu-project/qemu/-/issues/2295

By akihiko.odaki at April 27, 2024, 8:07 a.m. (reply...)

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